Magnetic memory device

ABSTRACT

The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

BACKGROUND

Magnetoresistive random-access memory (MRAM) is a type of non-volatilerandom-access memory that stores data in magnetic domains. MRAM has theadvantages of low power consumption and high data retention. MRAM can beused in microcontroller units (MCUs), internet of things (IOTs), andwearable devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures.

FIG. 1 is a diagram of a magnetic memory device, in accordance with someembodiments.

FIGS. 2A-2D illustrate a magnetic memory device, in accordance with someembodiments.

FIGS. 3A and 3B are diagrams of a magnetic tunneling junction, inaccordance with some embodiments.

FIGS. 4A and 4B are diagrams of a magnetic data cell, in accordance withsome embodiments.

FIGS. 5A and 5B are diagrams of a magnetic memory cell, in accordancewith some embodiments.

FIGS. 6A and 6B illustrate cross-sectional views of a magnetic datacell, in accordance with some embodiments.

FIG. 7 illustrates a top view of a magnetic sensing array, in accordancewith some embodiments.

FIG. 8 is an exemplary pattern of logical values in a magnetic sensingarray, in accordance with some embodiments.

FIGS. 9A and 9B are plots of flip rate with respect to magnetic fieldstrength, in accordance with some embodiments.

FIG. 10 is a diagram of test voltages provided by a voltage modulator,in accordance with some embodiments.

FIG. 11 is an exemplary pattern of logical values in an error checkarray, in accordance with some embodiments.

FIGS. 12A and 12B are plots of bit error rate with respect to a write 0voltage and a write 1 voltage, respectively, in accordance with someembodiments.

FIG. 13 is a plot of write bias with respect to external magnetic fieldstrength, in accordance with some embodiments.

FIG. 14 is a flow diagram of a method for operating a magnetic memorydevice, in accordance with some embodiments.

FIG. 15 is a flow diagram of a method for calculating a bit error rate,in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the processfor forming a first feature over a second feature in the descriptionthat follows may include embodiments in which the first and secondfeatures are formed in direct contact, and may also include embodimentsin which additional features may be formed between the first and secondfeatures, such that the first and second features may not be in directcontact. As used herein, the formation of a first feature on a secondfeature means the first feature is formed in direct contact with thesecond feature. In addition, the present disclosure may repeat referencenumerals and/or letters in the various examples. This repetition doesnot in itself dictate a relationship between the embodiments and/orconfigurations discussed herein.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. The spatially relative termsare intended to encompass different orientations of the device in use oroperation in addition to the orientation depicted in the figures. Theapparatus may be otherwise oriented (rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein maylikewise be interpreted accordingly.

It is noted that references in the specification to “one embodiment,”“an embodiment,” “an example embodiment,” “exemplary,” etc., indicatethat the embodiment described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases do not necessarily refer to the same embodiment. Further,when a particular feature, structure or characteristic is described inconnection with an embodiment, it would be within the knowledge of oneskilled in the art to effect such feature, structure or characteristicin connection with other embodiments whether or not explicitlydescribed.

It is to be understood that the phraseology or terminology herein is forthe purpose of description and not of limitation, such that theterminology or phraseology of the present specification is to beinterpreted by those skilled in relevant art(s) in light of theteachings herein.

In some embodiments, the terms “about” and “substantially” can indicatea value of a given quantity that varies within 5% of the value (e.g.,+1%, ±2%, +3%, ±4%, +5% of the value). These values are merely examplesand are not intended to be limiting. The terms “about” and“substantially” can refer to a percentage of the values as interpretedby those skilled in relevant art(s) in light of the teachings herein.

The discussion of elements in FIGS. 1, 2A-2D, 3A, 3B, 4A, 4B, 5A, 5B,6A, 6B, 7, 8, 9A, 9B, 10, 11, 12A, 12B, and 13 with the same annotationsapplies to each other, unless mentioned otherwise.

Magnetoresistive random-access memory (MRAM) is a type of non-volatilerandom-access memory that stores data in magnetic domains. MRAM caninclude a number of magnetic memory cells. Each magnetic memory cell caninclude a magnetic data cell and a reference cell. The magnetic datacell can include a magnetic tunneling junction and one or twotransistors. The magnetic tunneling junction can include a nonmagneticlayer interposed between a first magnetic layer and a second magneticlayer. The first magnetic layer can have a fixed magnetizationdirection. The second magnetic layer can have two magnetizationdirections. When the magnetization direction of the second magneticlayer is parallel to the fixed magnetization direction of the firstmagnetic layer, a first logical value (e.g., a logical 0) can be stored.When the magnetization direction of the second magnetic layer isantiparallel to the fixed magnetization direction of the first magneticlayer, a second logical value (e.g., a logical 1) can be stored.

To change from the first logical value (e.g., a logical 0) to the secondlogical value (e.g., a logical 1), a first write voltage (e.g., a write1 voltage) can be applied to change the magnetization direction of thesecond magnetic layer from being parallel to being antiparallel to thefixed magnetization direction of the first magnetic layer. To changefrom the second logical value (e.g., a logical 1) to the first logicalvalue (e.g., a logical 0), a second write voltage (e.g., a write 0voltage) can be applied to change the magnetization direction of thesecond magnetic layer from being antiparallel to being parallel to thefixed magnetization direction of the first magnetic layer. To read thefirst logical value (e.g., a logical 0) or the second logical value(e.g., a logical 1), a read voltage can be applied. Once themagnetization of the second magnetic layer is completed, themagnetization can remain for a substantially long time. Therefore, MRAMcan have very high data retention. Furthermore, unlike in dynamicrandom-access memory (DRAM) where the data is periodically refreshed, orin static random-access memory (SRAM) where a power supply must becontinuously maintained, MRAM has the advantage of low power consumptionbecause there is no need to refresh the data. However, when an externalmagnetic field exists, such as a permanent magnet, if the write voltageof the MRAM remains the same, the external magnetic field can causewrite errors. The write errors can reduce MRAM data storage accuracy andreliability.

The present disclosure provides an example magnetic memory device withimproved data storage accuracy and reliability and an example method foroperating the same. The magnetic memory device can include a magneticsensing array. The magnetic sensing array can include a number ofmagnetic sensing elements with initial logical values of 0 or 1 arrangedin a pattern. The magnetic sensing array can sense an external magneticfield strength based on a flip rate of the initial logical values underthe influence of the external magnetic field. If the sensed externalmagnetic field strength is below a threshold magnetic field strength,the external magnetic field has no effect on data storage accuracy andreliability and the write voltage of the magnetic memory device canremain the same. In some embodiments, for example, if the sensedexternal magnetic field strength is below about 100 Oersted (Oe), thewrite voltage of the magnetic memory device can remain the same. If thesensed external magnetic field strength is above the threshold magneticfield strength, the external magnetic field can reduce data storageaccuracy and reliability and the write voltage of the magnetic memorydevice may need to be adjusted. In some embodiments, for example, if thesensed external magnetic field strength is between about 100 Oe andabout 1000 Oe, the write voltage of the magnetic memory device will needto be adjusted. If the sensed external magnetic field strength is aboveabout 1000 Oe, write operations to the magnetic memory device with anywrite voltage can cause data loss and errors. Therefore, new writeoperations should not be performed. Data already stored in the magneticmemory device can have a higher tolerance for the external magneticfield and read operations can cause less volatility of the data thanwrite operations. Therefore, read operations of data already stored inthe magnetic memory device can be performed.

To adjust the write voltage of the magnetic memory device, the magneticmemory device can include a voltage modulator and an error check array.The voltage modulator can provide a test voltage different from acurrent write voltage of the magnetic memory device. The error checkarray can use the test voltage as the write voltage to write logicalvalues and provide a bit error rate. In some embodiments, the testvoltage can be repeated between about 2 and 10000 cycles to improve theaccuracy of the bit error rate. If the bit error rate is equal to orless than a threshold bit error rate, the test voltage can be used asthe new write voltage under the influence of the sensed externalmagnetic field. If the bit error rate is greater than the threshold biterror rate, the test voltage is not a suitable write voltage under theinfluence of the sensed external magnetic field and a new test voltagewill need to be tested. In some embodiments, between about 3 and about100 test voltages can be tested to find the suitable new write voltage.

In some embodiments, the external magnetic field can be sensed beforeevery write operation. In some embodiments, the external magnetic fieldcan be sensed periodically, such as after 10 write operations, after 100write operations, or after 1000 write operations. The magnetic memorydevice with the magnetic sensing array, the voltage modulator, and theerror check array can adjust write voltages according to externalmagnetic field strengths. The adjusted write voltages can improve datastorage accuracy and reliability.

FIG. 1 is a diagram of a magnetic memory device 100, according to someembodiments. Magnetic memory device 100 can include a magnetic sensingarray 102, a control unit 104, a voltage modulator 106, an error checkarray 108, and a storage array 110. Control unit 104 can includetransistors, resistors, capacitors, and other components. Control unit104 can receive and send data and command signals between control unit104 and magnetic sensing array 102, voltage modulator 106, error checkarray 108, and storage array 110. Magnetic sensing array 102 can sensean external magnetic field strength. In some embodiments, magneticsensing array 102 can sense the external magnetic field strength basedon a flip rate of initial logical values of magnetic sensing array 102under the influence of the external magnetic field. Control unit 104 cansend a command signal to command magnetic sensing array 102 to sense theexternal magnetic field strength. The command signal can be sent beforeevery write operation or periodically such as after a certain number ofwrite operations. The sensed external magnetic field strength can besent from magnetic sensing array 102 to control unit 104. Control unit104 can compare the sensed magnetic field strength with a thresholdmagnetic field strength. If control unit 104 determines that the sensedmagnetic field strength is below the threshold magnetic field strength,control unit 104 can send a write signal to write to storage array 110with a current write voltage. If control unit 104 determines that thesensed magnetic field strength is above the threshold magnetic fieldstrength, control unit 104 can adjust the current write voltage. Controlunit 104 can command voltage modulator 106 and error check array 108 toadjust the current write voltage.

Voltage modulator 106 can include transistors, resistors, capacitors,and other components. In response to a determination that the sensedmagnetic field strength is above the threshold magnetic field strength,control unit 104 can send a command signal to voltage modulator 106 toprovide a test voltage. The test voltage can be sent from voltagemodulator 106 to error check array 108 and control unit 104. Controlunit 104 can send a command signal to error check array 108 to checkwhether the test voltage provided by voltage modulator 106 can be asuitable new write voltage under the influence of the sensed externalmagnetic field. Error check array 108 can write the same logical valuesto a number of error check elements as the initial logical values of theerror check elements. Control unit 104 can read the initial logicalvalues of the error check elements. Control unit 104 can read thewritten logical values of the error check elements. Control unit 104 cancompare the written logical values and the initial logical values tocalculate a bit error rate. In some embodiments, error check array 108can calculate the bit error rate and provide the bit error rate tocontrol unit 104.

Control unit 104 can compare the bit error rate with a threshold biterror rate. If control unit 104 determines that the bit error rate isequal to or less than the threshold bit error rate, the test voltage canbe a suitable new write voltage. Control unit 104 can adjust the currentwrite voltage to the test voltage and send a write signal to write tostorage array 110 with the adjusted write voltage. If control unit 104determines that the bit error rate is greater than the threshold biterror rate, the test voltage is not a suitable new write voltage.Control unit 104 can send a command signal to voltage modulator 106 toprovide a new test voltage. Control unit 104 can command voltagemodulator 106 to provide as many test voltages as needed until asuitable new write voltage is obtained. In some embodiments, controlunit 104 can send one command signal to voltage modulator 106, andvoltage modulator 106 can provide more than one test voltage afterexecuting the one command signal. Storage array 110 can store data inmagnetic domains using the current write voltage or the adjusted writevoltage, depending on the command signals from control unit 104. Controlunit 104 can also send a read signal to read storage array 110.

FIGS. 2A-2D illustrate a magnetic memory device, such as magnetic memorydevice 100, according to some embodiments. The magnetic memory devicecan include magnetic sensing array 102, control unit 104, voltagemodulator 106, error check array 108, and storage array 110. In someembodiments, magnetic sensing array 102, error check array 108, andstorage array 110 can each include a number of magnetic memory cells. Insome embodiments, magnetic sensing array 102, error check array 108, andstorage array 110 can include magnetic memory cells in differentsections of the same array of magnetic memory cells. For example,magnetic sensing array 102 can include a section 102 of an array ofmagnetic memory cells. Error check array 108 can include sections 108 ofthe array of magnetic memory cells. Storage array 110 can include theremaining portions 110 of the array of magnetic memory cells. In someembodiments, magnetic sensing array 102 can occupy less than about 1% ofthe array of magnetic memory cells. In some embodiments, magneticsensing array 102 can include a section of magnetic memory cells thatare more sensitive to external magnetic fields. For example, magneticmemory cells within magnetic sensing array 102 can flip logical valuesunder the influence of external magnetic fields more easily than othermagnetic memory cells within storage array 110. This can allow magneticsensing array 102 to sense external magnetic fields more accurately andquickly before the external magnetic fields cause data discrepancy instorage array 110. In some embodiments, magnetic sensing array 102 canbe located at an upper left corner of the array of magnetic memorycells.

Error check array 108 can be placed at different locations on the arrayof magnetic memory cells. By placing error check array 108 at differentlocations, a bit error rate corresponding to a test voltage can be morerepresentative over the entire array of magnetic memory cells. Referringto FIG. 2A, error check array 108 can include two vertical strips. Thefirst vertical strip can be placed toward the lower left end of thearray of magnetic memory cells. The second vertical strip can be placedtoward the lower right end of the array of magnetic memory cells.Referring to FIG. 2B, error check array 108 can include two horizontalstrips. The first horizontal strip can be placed toward the upper centerof the array of magnetic memory cells. The second horizontal strip canbe placed toward the lower center of the array of magnetic memory cells.Referring to FIG. 2C, error check array 108 can include two horizontalstrips and two vertical strips. The first horizontal strip can be placedtoward the upper center of the array of magnetic memory cells. Thesecond horizontal strip can be placed toward the lower center of thearray of magnetic memory cells. The first vertical strip can be placedtoward the lower left end of the array of magnetic memory cells. Thesecond vertical strip can be placed toward the lower right end of thearray of magnetic memory cells. Referring to FIG. 2D, error check array108 can include two square sections. The first square section can beplaced toward the upper left corner of the array of magnetic memorycells. The second square section can be placed toward the lower rightcorner of the array of magnetic memory cells.

FIGS. 3A and 3B are diagrams of a magnetic tunneling junction 308,according to some embodiments. Magnetic tunneling junction 308 caninclude a nonmagnetic layer 304 interposed between a first magneticlayer 306 and a second magnetic layer 302. First magnetic layer 306 andsecond magnetic layer 302 can have magnetization directions. Referringto FIG. 3A, first magnetic layer 306 and second magnetic layer 302 canhave perpendicular magnetization directions. First magnetic layer 306can have a fixed magnetization direction 314. Second magnetic layer 302can have a first magnetization direction 312 and a second magnetizationdirection 310. When second magnetic layer 302 has first magnetizationdirection 312, which is parallel to fixed magnetization direction 314 offirst magnetic layer 306, a logical 0 can be stored. When secondmagnetic layer 302 has second magnetization direction 310, which isantiparallel to fixed magnetization direction 314 of first magneticlayer 306, a logical 1 can be stored. To change a logical 0 to a logical1, a write 1 voltage can be applied to change the magnetizationdirection of second magnetic layer 302 from first magnetizationdirection 312 to second magnetization direction 310. To change a logical1 to a logical 0, a write 0 voltage can be applied to change themagnetization direction of second magnetic layer 302 from secondmagnetization direction 310 to first magnetization direction 312.

Referring to FIG. 3B, first magnetic layer 306 and second magnetic layer302 can have in-plane magnetization directions. First magnetic layer 306can have a fixed magnetization direction 320. Second magnetic layer 302can have a first magnetization direction 318 and a second magnetizationdirection 316. When second magnetic layer 302 has first magnetizationdirection 318, which is parallel to fixed magnetization direction 320 offirst magnetic layer 306, a logical 0 can be stored. When secondmagnetic layer 302 has second magnetization direction 316, which isantiparallel to fixed magnetization direction 320 of first magneticlayer 306, a logical 1 can be stored. To change a logical 0 to a logical1, a write 1 voltage can be applied to change the magnetizationdirection of second magnetic layer 302 from first magnetizationdirection 318 to second magnetization direction 316. To change a logical1 to a logical 0, a write 0 voltage can be applied to change themagnetization direction of second magnetic layer 302 from secondmagnetization direction 316 to first magnetization direction 318. Insome embodiments, magnetic tunneling junctions 308 with perpendicularmagnetization directions can be used. In some embodiments, magnetictunneling junctions 308 with in-plane magnetization directions can beused. In some embodiments, magnetic tunneling junctions 308 withperpendicular magnetization directions and magnetic tunneling junctions308 with in-plane magnetization directions can be used together.

FIGS. 4A and 4B are diagrams of a magnetic data cell, according to someembodiments. Referring to FIG. 4A, the magnetic data cell can includeone magnetic tunneling junction 308, such as shown in FIG. 3A or 3B, andone transistor 408. The magnetic data cell can include a bit line 404, aword line 406, and a select line 402. Referring to FIG. 4B, the magneticdata cell can include one magnetic tunneling junction 308, such as shownin FIG. 3A or 3B, and two transistors 408. The magnetic data cell caninclude bit line 404, select line 402, a write word line 410, and a readword line 412. The magnetic data cell can include a heavy metal 414.Heavy metal 414 can generate spin current to control the magnetizationdynamics of magnetic tunneling junction 308 by spin-orbit torque. Heavymetal 414 can improve the performance of magnetic tunneling junction308.

FIGS. 5A and 5B are diagrams of a magnetic memory cell, according tosome embodiments. Referring to FIG. 5A, the magnetic memory cell caninclude a magnetic data cell 510, which can include one magnetictunneling junction and one transistor such as shown in FIG. 4A. In someembodiments, magnetic data cell 510 can include one magnetic tunnelingjunction and two transistors such as shown in FIG. 4B. The magneticmemory cell can include a reference cell 512. Reference cell 512 caninclude two magnetic tunneling junctions in a permanent parallel state,two magnetic tunneling junctions in a permanent antiparallel state, andone transistor. The magnetic memory cell can include select line 402,word line 406, and bit line 404. The magnetic memory cell can include acomparison circuit 508. Comparison circuit 508 can include loadtransistors 504, clamp transistors 506, and a voltage comparator 502.

Referring to FIG. 5B, the magnetic memory cell can include magnetic datacell 510, select line 402, word line 406, bit line 404, comparisoncircuit 508, and a reference cell 514. Reference cell 514 can includeeight magnetic tunneling junctions in a permanent parallel state, eightmagnetic tunneling junctions in a permanent antiparallel state, and onetransistor. Magnetic memory cells as shown in FIG. 5A or 5B can be themagnetic memory cells that constitute the array of magnetic memory cellsas shown in FIGS. 2A-2D. Therefore, magnetic sensing array 102, errorcheck array 108, and storage array 110 can include magnetic memory cellsas shown in FIG. 5A or 5B.

FIGS. 6A and 6B illustrate cross-sectional views of magnetic data cells602 and 604, according to some embodiments. Referring to FIG. 6A,magnetic data cell 602 or 604 can include one magnetic tunnelingjunction 308 and one transistor. In some embodiments, FIG. 4A can be adiagram of magnetic data cell 602 or 604. In some embodiments, magneticdata cell 602 or 604 can include one magnetic tunneling junction 308 andtwo transistors (not shown in FIG. 6A). In some embodiments, FIG. 4B canbe a diagram of magnetic data cell 602 or 604. The transistor caninclude a gate structure 610, a source 608, and a drain 606. Magneticdata cell 602 or 604 can include a first metal layer 616, a second metallayer 618, . . . , an Nth metal layer 620, and an (N+1)th metal layer622. First metal layer 616 can include a metal via structure 612 and ametal line 614. Magnetic tunneling junction 308 can be interposedbetween Nth metal layer 620 and (N+1)th metal layer 622. In someembodiments, magnetic tunneling junction 308 can be located on the samelevel as the transistor. In some embodiments, magnetic tunnelingjunction 308 can be interposed between metal layers other than Nth metallayer 620 and (N+1)th metal layer 622. A distance L1 between adjacentmagnetic data cell 602 and magnetic data cell 604 can be between about200 nm and about 500 nm, between about 100 nm and about 800 nm, andbetween about 10 nm and about 1000 nm. If distance L1 is greater thanabout 1000 nm, the density of magnetic data cells 602 and 604 can be toolow. The density of magnetic data cells 602 and 604 can be too low ifthe bit density of the array of magnetic memory cells is below about 50kb/mm². If distance L1 is less than about 10 nm, the manufacturingdifficulty can be too great and the manufacturing cost can be too high.

Referring to FIG. 6B, magnetic tunneling junction 308 can have a stackedstructure including nonmagnetic layer 304, first magnetic layer 306, andsecond magnetic layer 302. Nonmagnetic layer 304 can include anonmagnetic material including magnesium oxide (MgO_(x)), aluminum oxide(AlO_(x)), copper (Cu), aluminum (Al), ruthenium (Ru), Iridium (Ir), andcombinations thereof. First magnetic layer 306 and second magnetic layer302 can include a magnetic material including iron (Fe), cobalt (Co),nickel (Ni), chromium (Cr), alloys of Fe, Co, Ni, and/or Cr, compoundscontaining Fe, Co, Ni, and/or Cr, and combinations thereof. A topcontact 626 can be disposed on top of magnetic tunneling junction 308and a bottom contact 624 can be disposed below magnetic tunnelingjunction 308. Top contact 626 and bottom contact 624 can include aconductive material including Cu, tungsten (W), and combinationsthereof. Magnetic tunneling junction 308 can have a width W1 betweenabout 200 nm and about 500 nm, between about 100 nm and about 800 nm,and between about 10 nm and about 1000 nm. If width W1 is greater thanabout 1000 nm, the density of magnetic data cells 602 and 604 can be toolow. The density of magnetic data cells 602 and 604 can be too low ifthe bit density of the array of magnetic memory cells is below about 50kb/mm². If width W1 is less than about 10 nm, the manufacturingdifficulty can be too great and the manufacturing cost can be too high.In some embodiments, magnetic tunneling junction 308 can have a taperedstructure. For example, magnetic tunneling junction 308 can be narrowertoward the top and wider toward the bottom.

FIG. 7 illustrates a top view of magnetic sensing array 102, accordingto some embodiments. Magnetic sensing array 102 can include a number ofmagnetic sensing elements arranged in a pattern. In some embodiments,magnetic sensing array 102 can include a number of magnetic data cells602 arranged in a pattern. In some embodiments, magnetic sensing array102 can include a number of magnetic memory cells as shown in FIGS. 5Aand 5B arranged in a pattern. The magnetic sensing elements can have acircular shape as shown in FIG. 7 . The magnetic sensing elements canhave other shapes including a square shape, a triangular shape, arectangular shape, an oval shape, and combinations thereof. The shape ofthe magnetic sensing elements can affect the sensitivity of magneticsensing array 102 to sense external magnetic fields. For example,circular magnetic sensing elements can have a smaller area than squaremagnetic sensing elements when the diameter of the circular magneticsensing elements is the same as the side length of the square magneticsensing elements. Therefore, magnetic sensing array 102 with circularmagnetic sensing elements can have a lower sensitivity than magneticsensing array 102 with square magnetic sensing elements when thediameter of the circular magnetic sensing elements is the same as theside length of the square magnetic sensing elements.

Each magnetic sensing element can have a width W2 between about 50 nmand about 100 nm, between about 30 nm and about 150 nm, and betweenabout 10 nm and about 200 nm. If width W2 is greater than about 200 nm,the density of the magnetic sensing elements can be too low. The densityof the magnetic sensing elements can be too low if the bit density ofmagnetic sensing array 102 is below about 50 kb/mm². If width W2 is lessthan about 10 nm, the sensitivity of magnetic sensing array 102 can betoo low. Adjacent columns of magnetic sensing elements can have aspacing W3 between about 200 nm and about 500 nm, between about 100 nmand about 800 nm, and between about 10 nm and about 1000 nm. If spacingW3 is greater than about 1000 nm, the sensitivity of magnetic sensingarray 102 can be too low and the density of the magnetic sensingelements can be too low. The density of the magnetic sensing elementscan be too low if the bit density of magnetic sensing array 102 is belowabout 50 kb/mm². If spacing W3 is less than about 10 nm, themanufacturing difficulty can be too great and the manufacturing cost canbe too high. Adjacent rows of magnetic sensing elements can have aspacing W4 between about 200 nm and about 500 nm, between about 100 nmand about 800 nm, and between about 10 nm and about 1000 nm. If spacingW4 is greater than about 1000 nm, the sensitivity of magnetic sensingarray 102 can be too low and the density of the magnetic sensingelements can be too low. The density of the magnetic sensing elementscan be too low if the bit density of magnetic sensing array 102 is belowabout 50 kb/mm². If spacing W4 is less than about 10 nm, themanufacturing difficulty can be too great and the manufacturing cost canbe too high.

FIG. 8 is an exemplary pattern of logical values in magnetic sensingarray 102, according to some embodiments. The pattern can includelogical values of 0 or 1 randomly assigned and stored in the magneticsensing elements of magnetic sensing array 102. The pattern can includerows and columns of logical values of 0 or 1 stored in the magneticsensing elements. The pattern can include a geometric pattern such as acheckerboard pattern or an inverse checkerboard pattern. Control unit104 can send a read signal to magnetic sensing array 102 to read theinitial logical values of the magnetic sensing elements. If an externalmagnetic field exists, one or more logical values of the magneticsensing elements can be flipped by the external magnetic field. Forexample, one or more logical values can change from a logical 0 to alogical 1, and one or more logical values can change from a logical 1 toa logical 0. Control unit 104 can send another read signal to magneticsensing array 102 to read the logical values of the magnetic sensingelements after being influenced by the external magnetic field. Controlunit 104 can compare the initial logical values and the logical valuesafter being influenced by the external magnetic field to calculate aflip rate. The flip rate can be calculated by the total number offlipped logical values divided by the total number of magnetic sensingelements. In some embodiments, after each determination of a flip rate,the logical values in magnetic sensing array 102 can be reset to theinitial logical values. In some embodiments, the logical values inmagnetic sensing array 102 can remain as what have been influenced bythe external magnetic field. To sense a new external magnetic field,control unit 104 can send a read signal to magnetic sensing array 102 toread the influenced logical values first as the new baseline logicalvalues to calculate a new flip rate.

FIGS. 9A and 9B are plots of flip rate with respect to magnetic fieldstrength, according to some embodiments. Referring to FIG. 9A, magneticsensing array 102 can include several sections of magnetic sensingelements and each section can sense a range of magnetic field strengths.Magnetic sensing elements can be designed with different shapes, sizes,and spacings such that each section of the magnetic sensing elements canhave a different sensitivity to a different range of magnetic fieldstrengths. For example, plot 902 can be flip rate with respect tomagnetic field strength for the range of magnetic field strengths belowabout H1; plot 904 can be flip rate with respect to magnetic fieldstrength for the range of magnetic field strengths between about H1 andabout H2; plot 906 can be flip rate with respect to magnetic fieldstrength for the range of magnetic field strengths between about H2 andabout H3. Cumulatively, the several sections of magnetic sensingelements can sense a wide range of magnetic field strengths. An externalmagnetic field can be sensed by a corresponding section of magneticsensing elements. Within each range, as the external magnetic fieldstrength increases, the flip rate increases. Based on the correlationbetween the flip rate and the magnetic field strength, the externalmagnetic field strength can be determined. Plot 908 can be flip rate ofstorage array 110 with respect to magnetic field strength. Logicalvalues in storage array 110 can flip when the range of magnetic fieldstrengths is above about H3. Logical values in magnetic sensing array102 can flip at a lower magnetic field strength than logical values instorage array 110. This can ensure that magnetic sensing array 102senses the external magnetic field before the external magnetic fieldreaches a level that reduces data storage integrity.

Referring to FIG. 9B, magnetic sensing array 102 can include one sectionof magnetic sensing elements that can sense a wide range of magneticfield strengths. For example, plot 910 can be flip rate with respect tomagnetic field strength for the range of magnetic field strengths frombelow about H1 to above about H3. As the external magnetic fieldstrength increases, the flip rate increases. A look-up table can bestored in control unit 104. The look-up table can detail each flip ratecorresponding to each external magnetic field strength. Once a flip rateis obtained, control unit 104 can refer to the look-up table todetermine an external magnetic field strength. Plot 908 can be flip rateof storage array 110 with respect to magnetic field strength. Logicalvalues in storage array 110 can flip at a higher magnetic field strengththan logical values in magnetic sensing array 102. This can ensure thatmagnetic sensing array 102 senses the external magnetic field before theexternal magnetic field reaches a level that reduces data storageintegrity.

FIG. 10 is a diagram of test voltages 1002 and 1004 provided by voltagemodulator 106, according to some embodiments. Test voltage 1002 caninclude a write 0 voltage 1006, a read voltage 1008, and a write 1voltage 1010. Test voltage 1004 can include a write 0 voltage 1012 thatis greater than write 0 voltage 1006 in absolute value, read voltage1008, and a write 1 voltage 1014 that is greater than write 1 voltage1010 in absolute value. External magnetic fields affect read operationsto a lesser degree than external magnetic fields affect writeoperations. Therefore, read voltage 1008 can stay the same in testvoltages 1002 and 1004. In some embodiments, test voltages 1002 and 1004can omit read voltages. In some embodiments, test voltages 1002 and 1004can include a write 0 voltage or a write 1 voltage instead of both.

When an external magnetic field strength is above a threshold magneticfield strength, voltage modulator 106 can provide test voltage 1002.Error check array 108 can use write 0 voltage 1006 of test voltage 1002to write logical values of 0 to the error check elements. Error checkarray 108 or control unit 104 can calculate a bit error rate of writinglogical values of 0. If the bit error rate of writing logical values of0 is equal to or less than a threshold bit error rate, write 0 voltage1006 can be used as the new write 0 voltage for magnetic memory device100. Similarly, error check array 108 can use write 1 voltage 1010 oftest voltage 1002 to write logical values of 1 to the error checkelements. Error check array 108 or control unit 104 can calculate a biterror rate of writing logical values of 1. If the bit error rate ofwriting logical values of 1 is equal to or less than a threshold biterror rate, write 1 voltage 1010 can be used as the new write 1 voltagefor magnetic memory device 100. In some embodiments, test voltage 1002can be repeated between about 500 and about 5000 cycles, between about100 and about 8000 cycles, and between about 2 and about 10000 cycles.The repetition of test voltage 1002 can increase the accuracy of the biterror rate calculation. If the repetition is less than about 2 cycles,the accuracy of the bit error rate calculation can be too low. If therepetition is greater than about 10000 cycles, the time used to obtainthe bit error rate can be too great.

If the bit error rate corresponding to test voltage 1002 is greater thanthe threshold bit error rate, test voltage 1002 cannot be used as thenew write voltage for magnetic memory device 100. Voltage modulator 106can continue to provide test voltage 1004 with different absolute valuesof write voltages. Error check array 108 can use write 0 voltage 1012 oftest voltage 1004 to write logical values of 0 to the error checkelements. Error check array 108 or control unit 104 can calculate a biterror rate of writing logical values of 0. If the bit error rate ofwriting logical values of 0 is equal to or less than the threshold biterror rate, write 0 voltage 1012 can be used as the new write 0 voltagefor magnetic memory device 100. Similarly, error check array 108 can usewrite 1 voltage 1014 of test voltage 1004 to write logical values of 1to the error check elements. Error check array 108 or control unit 104can calculate a bit error rate of writing logical values of 1. If thebit error rate of writing logical values of 1 is equal to or less thanthe threshold bit error rate, write 1 voltage 1014 can be used as thenew write 1 voltage for magnetic memory device 100. Test voltage 1004can be similarly repeated between about 2 and about 10000 cycles toincrease the accuracy of the bit error rate calculation.

If the bit error rate corresponding to test voltage 1004 is greater thanthe threshold bit error rate, test voltage 1004 cannot be used as thenew write voltage for magnetic memory device 100. Voltage modulator 106can continue to provide more test voltages with different absolutevalues of write voltages. In some embodiments, voltage modulator 106 canprovide more test voltages with incrementally greater absolute values,with incrementally smaller absolute values, or with oscillating absolutevalues. In some embodiments, voltage modulator 106 can provide betweenabout 10 and about 50 test voltages, between about 5 and about 80 testvoltages, and between about 3 and about 100 test voltages. If the numberof test voltages provided is less than about 3, a new write voltage ofmagnetic memory device 100 may not be found if all of the test voltagesfail to pass the threshold bit error rate. If the number of testvoltages provided is greater than about 100, the time used to obtain thenew write voltage of magnetic memory device 100 can be too great. Insome embodiments, voltage modulator 106 can continue to provide testvoltages until a suitable new write voltage of magnetic memory device100 is obtained.

FIG. 11 is an exemplary pattern of logical values in error check array108, according to some embodiments. The pattern can include logicalvalues of 0 or 1 randomly assigned and stored in the error checkelements of error check array 108. The pattern can include rows andcolumns of logical values of 0 or 1 stored in the error check elements.Two rows of logical values of 0 or 1 stored in the error check elementsare shown in FIG. 11 . The pattern can include a geometric pattern, suchas a checkerboard pattern or an inverse checkerboard pattern. Tocalculate a bit error rate, control unit 104 can send a read signal toerror check array 108 to read the initial logical values of the errorcheck elements. After voltage modulator 106 provides a test voltage,such as test voltage 1002 or 1004, error check array 108 can use thetest voltage as a write voltage to write the same logical value intoeach error check element. Control unit 104 can send a read signal toerror check array 108 to read the written logical values. Control unit104 can compare the written logical values and the initial logicalvalues. If a written logical value is different from an initial logicalvalue, a bit error has occurred. If there is one cycle of writeoperations, the total number of write operations is the same as thetotal number of error check elements. The total number of bit errorsdivided by the total number of error check elements can be the bit errorrate. If the test voltage is repeated, the total number of writeoperations can be the total number of error check elements times thenumber of repeats. The bit error rate can be calculated by the totalnumber of bit errors divided by the total number of write operations. Insome embodiments, error check array 108 can calculate the bit error rateand provide the bit error rate to control unit 104. Control unit 104 cancompare the bit error rate with a threshold bit error rate. In someembodiments, after each test voltage, the logical values in the errorcheck elements can be reset to the initial logical values. In someembodiments, the logical values in the error check elements can remainas what have been written using the test voltage as the write voltage.For a new test voltage, control unit 104 can send a read signal to errorcheck array 108 to read the written logical values first as the newbaseline logical values to calculate a new bit error rate.

FIGS. 12A and 12B are plots of bit error rate with respect to a write 0voltage and a write 1 voltage, respectively, according to someembodiments. Referring to FIG. 12A, plot 1204 can be a bit error ratewith respect to the write 0 voltage when there is no external magneticfield. As the write 0 voltage increases, the bit error rate decreases.Once the bit error rate is equal to a threshold bit error rate 1208, anywrite 0 voltage greater than the threshold write 0 voltage can be used.However, it can be more reliable to provide a lower write voltage than ahigher write voltage. Therefore, a write 0 voltage that is closer to thethreshold write 0 voltage can be more reliably implemented. Plot 1202can be a bit error rate with respect to the write 0 voltage when thereis an external magnetic field with a first polarity such as +H. If thewrite 0 voltage is kept at the same write 0 voltage when there is noexternal magnetic field, the bit error rate when there is +H would begreater than threshold bit error rate 1208. To reduce the bit errorrate, the write 0 voltage must be increased. Plot 1206 can be a biterror rate with respect to the write 0 voltage when there is an externalmagnetic field with a second polarity such as −H. If the write 0 voltageis kept at the same write 0 voltage when there is no external magneticfield, the bit error rate when there is −H would be less than thresholdbit error rate 1208. However, to improve the reliability of implementingthe write 0 voltage when there is −H, the write 0 voltage should bedecreased.

Referring to FIG. 12B, plot 1204 can be a bit error rate with respect tothe write 1 voltage when there is no external magnetic field. As thewrite 1 voltage increases, the bit error rate decreases. Once the biterror rate is equal to threshold bit error rate 1208, any write 1voltage greater than the threshold write 1 voltage can be used. However,it can be more reliable to provide a lower write voltage than a higherwrite voltage. Therefore, a write 1 voltage that is closer to thethreshold write 1 voltage can be more reliably implemented. Plot 1202can be a bit error rate with respect to the write 1 voltage when thereis an external magnetic field with a first polarity such as +H. If thewrite 1 voltage is kept at the same write 1 voltage when there is noexternal magnetic field, the bit error rate when there is +H would beless than threshold bit error rate 1208. However, to improve thereliability of implementing the write 1 voltage when there is +H, thewrite 1 voltage should be decreased. Plot 1206 can be a bit error ratewith respect to the write 1 voltage when there is an external magneticfield with a second polarity such as −H. If the write 1 voltage is keptat the same write 1 voltage when there is no external magnetic field,the bit error rate when there is −H would be greater than threshold biterror rate 1208. To reduce the bit error rate, the write 1 voltage mustbe increased. When there is +H, the write 0 voltage should be increasedand the write 1 voltage should be decreased to maintain the bit errorrate at the same level. When there is −H, the write 0 voltage should bedecreased and the write 1 voltage should be increased to maintain thebit error rate at the same level.

FIG. 13 is a plot of write bias with respect to external magnetic fieldstrength, according to some embodiments. Plot 1302 can be write biaswith respect to external magnetic field strength. As the externalmagnetic field strength increases, the write bias will need to beincreased. For example, when the external magnetic field strengthincreases, a larger absolute value of the write 0 voltage and the write1 voltage must be adjusted.

FIG. 14 is a flow diagram of a method 1400 for operating magnetic memorydevice 100, according to some embodiments. Additional operations can beperformed between the various operations of method 1400 and are omittedfor simplicity. These additional operations are within the spirit andthe scope of this disclosure. Moreover, not all operations may berequired to perform the disclosure provided herein. Additionally, someof the operations can be performed simultaneously or in a differentorder than the ones shown in FIG. 14 . It is understood that additionaloperations can be performed before, during, and after method 1400, andthat some other operations may only be briefly described herein.

In operation 1402, an external magnetic field strength can be sensed.The external magnetic field strength can be sensed by magnetic sensingarray 102. Magnetic sensing array 102 can include a number of magneticsensing elements with initial logical values of 0 or 1 arranged in apattern. When an external magnetic field exists, one or more magneticsensing elements can flip their logical values, such as changing from alogical 0 to a logical 1 or changing from a logical 1 to a logical 0.The higher the external magnetic field strength is, the greater the fliprate is. Therefore, magnetic sensing array 102 can sense the externalmagnetic field strength based on the flip rate. A sensitivity ofmagnetic sensing array 102 to sense the external magnetic field strengthcan depend on a shape or a size of the magnetic sensing elements and aspacing between the adjacent magnetic sensing elements. In someembodiments, magnetic sensing array 102 can include one or more magneticsensing sections and each magnetic sensing section can sense a range ofexternal magnetic field strengths. Cumulatively, the one or moremagnetic sensing sections can sense a wide range of external magneticfield strengths.

In operation 1404, a determination can be made whether the externalmagnetic field strength is above a threshold magnetic field strength.The determination can be made by control unit 104. If the sensedexternal magnetic field strength is below the threshold magnetic fieldstrength, the external magnetic field strength has no effect on datastorage accuracy and reliability. In operation 1414, a current writevoltage of magnetic memory device 100 can be kept. In operation 1416, awrite operation can be performed by magnetic memory device 100 using thecurrent write voltage. Data can be written into storage array 110. Insome embodiments, for example, if the sensed external magnetic fieldstrength is below about 100 Oe, the write voltage of magnetic memorydevice 100 can remain the same.

If the sensed external magnetic field strength is above the thresholdmagnetic field strength, the external magnetic field strength can reducedata storage accuracy and reliability and the write voltage of magneticmemory device 100 may need to be adjusted. In some embodiments, forexample, if the sensed external magnetic field strength is between about100 Oe and about 1000 Oe, the write voltage of magnetic memory device100 will need to be adjusted. If the sensed external magnetic fieldstrength is above about 1000 Oe, write operations to magnetic memorydevice 100 with any write voltage can cause data loss and errors.Therefore, new write operations should not be performed. Data alreadystored in the magnetic memory device can have a higher tolerance for theexternal magnetic field and read operations can cause less volatility ofthe data than write operations. Therefore, read operations of dataalready stored in the magnetic memory device can be performed.

In operation 1406, a test voltage different from the current writevoltage can be provided. The test voltage can be provided by voltagemodulator 106. The test voltage can include a write 0 voltage and/or awrite 1 voltage. In some embodiments, the test voltage can include aread voltage. In some embodiments, the test voltage can be repeatedbetween about 2 and about 10000 cycles.

In operation 1408, a bit error rate corresponding to the test voltagecan be provided. In some embodiments, the bit error rate can be providedby error check array 108. In some embodiments, the bit error rate can beprovided by control unit 104.

In operation 1410, a determination can be made whether the bit errorrate is equal to or less than a threshold bit error rate. Thedetermination can be made by control unit 104. If the bit error rate isequal to or less than the threshold bit error rate, in operation 1412,control unit 104 can adjust the write voltage of magnetic memory device100 from the current write voltage to the test voltage. In operation1416, a write operation can be performed by magnetic memory device 100using the adjusted write voltage. Data can be written into storage array110.

If the bit error rate is greater than the threshold bit error rate, thetest voltage is not suitable to be the new write voltage under theinfluence of the sensed external magnetic field and a new test voltagewill need to be tested. The method goes back to operation 1406 where anew test voltage can be provided. A bit error rate corresponding to thenew test voltage can be provided and compared to the threshold bit errorrate. If the bit error rate corresponding to the new test voltage isagain greater than the threshold bit error rate, method 1400 goes backto operation 1406 where yet another new test voltage can be provided.The loop can continue until a suitable test voltage can be used as thenew write voltage. In some embodiments, between about 3 and about 100test voltages can be tested to find the suitable new write voltage. Insome embodiments, after each test voltage, the logical values in theerror check elements can be reset to the initial logical values. In someembodiments, the logical values in the error check elements can remainas what have been written using the test voltage as the write voltage.For a new test voltage, control unit 104 can send a read signal to errorcheck array 108 to read the written logical values first as the newbaseline logical values to calculate a new bit error rate. After asuitable new write voltage is determined, in operation 1412, controlunit 104 can adjust the write voltage of magnetic memory device 100 fromthe current write voltage to the suitable new write voltage. Inoperation 1416, a write operation can be performed by magnetic memorydevice 100 using the adjusted write voltage. Data can be written intostorage array 110.

In some embodiments, method 1400 can be performed before every writeoperation. In some embodiments, method 1400 can be performedperiodically, such as after 10 write operations, after 100 writeoperations, or after 1000 write operations.

FIG. 15 is a flow diagram of a method 1500 for calculating a bit errorrate corresponding to a test voltage, according to some embodiments. Insome embodiments, method 1500 can include detailed operations to performoperation 1408 of method 1400 as shown in FIG. 14 .

In operation 1502, control unit 104 can send a read signal to errorcheck array 108 to read the initial logical values of the error checkelements. In operation 1504, after voltage modulator 106 provides a testvoltage, such as test voltage 1002 or 1004, error check array 108 canuse the test voltage as a write voltage to write the same logical valueinto each error check element. In operation 1506, control unit 104 cansend a read signal to error check array 108 to read the written logicalvalues. Control unit 104 can compare the written logical values and theinitial logical values. If a written logical value is different from aninitial logical value, a bit error has occurred. If there is one cycleof write operations, the total number of write operations is the same asthe total number of error check elements. The total number of bit errorsdivided by the total number of error check elements can be the bit errorrate. If the test voltage is repeated, the total number of writeoperations can be the total number of error check elements times thenumber of repeats. The bit error rate can be calculated by the totalnumber of bit errors divided by the total number of write operations. Insome embodiments, error check array 102 can calculate the bit error rateand provide the bit error rate to control unit 104.

The present disclosure provides an example magnetic memory device (e.g.,magnetic memory device 100) with improved data storage accuracy andreliability and an example method (e.g., methods 1400 and 1500) foroperating the same. The magnetic memory device can include a magneticsensing array (e.g., magnetic sensing array 102). The magnetic sensingarray can include a number of magnetic sensing elements with initiallogical values of 0 or 1 arranged in a pattern. The magnetic sensingarray can sense an external magnetic field strength based on a flip rateof the initial logical values under the influence of the externalmagnetic field. If the sensed external magnetic field strength is belowa threshold magnetic field strength, the external magnetic field has noeffect on data storage accuracy and reliability and the write voltage ofthe magnetic memory device can remain the same. In some embodiments, forexample, if the sensed external magnetic field strength is below about100 Oe, the write voltage of the magnetic memory device can remain thesame. If the sensed external magnetic field strength is above thethreshold magnetic field strength, the external magnetic field canreduce data storage accuracy and reliability and the write voltage ofthe magnetic memory device may need to be adjusted. In some embodiments,for example, if the sensed external magnetic field strength is betweenabout 100 Oe and about 1000 Oe, the write voltage of the magnetic memorydevice will need to be adjusted. If the sensed external magnetic fieldstrength is above about 1000 Oe, write operations to the magnetic memorydevice with any write voltage can cause data loss and errors. Therefore,new write operations should not be performed. Data already stored in themagnetic memory device can have a higher tolerance for the externalmagnetic field and read operations can cause less volatility of the datathan write operations. Therefore, read operations of data already storedin the magnetic memory device can be performed.

To adjust the write voltage of the magnetic memory device, the magneticmemory device can include a voltage modulator (e.g., voltage modulator106) and an error check array (e.g., error check array 108). The voltagemodulator can provide a test voltage (e.g., test voltage 1002) differentfrom a current write voltage of the magnetic memory device. The errorcheck array can use the test voltage as the write voltage to writelogical values and provide a bit error rate. In some embodiments, thetest voltage can be repeated between about 2 and 10000 cycles to improvethe accuracy of the bit error rate. If the bit error rate is equal to orless than a threshold bit error rate (e.g., threshold bit error rate1208), the test voltage can be used as the new write voltage under theinfluence of the sensed external magnetic field. If the bit error rateis greater than the threshold bit error rate, the test voltage is not asuitable write voltage under the influence of the sensed externalmagnetic field and a new test voltage (e.g., test voltage 1004) willneed to be tested. In some embodiments, between about 3 and about 100test voltages can be tested to find the suitable new write voltage.

In some embodiments, the external magnetic field can be sensed beforeevery write operation. In some embodiments, the external magnetic fieldcan be sensed periodically, such as after 10 write operations, after 100write operations, or after 1000 write operations. The magnetic memorydevice with the magnetic sensing array, the voltage modulator, and theerror check array can adjust write voltages according to externalmagnetic field strengths. The adjusted write voltages can improve datastorage accuracy and reliability.

In some embodiments, a magnetic memory device includes a magneticsensing array configured to sense an external magnetic field strength.The magnetic memory device further includes a voltage modulatorconfigured to, in response to the external magnetic field strength beinggreater than a threshold magnetic field strength, provide a test voltagedifferent from a current write voltage of the magnetic memory device.The magnetic memory device further includes an error check arrayconfigured to use the test voltage as a write voltage of the error checkarray and provide a bit error rate corresponding to the test voltage.The magnetic memory device further includes a control unit configured toadjust, based on the bit error rate being equal to or less than athreshold bit error rate, a write voltage of the magnetic memory devicefrom the current write voltage to the test voltage.

In some embodiments, a magnetic memory device includes a magneticsensing array including a number of magnetic sensing elements with firstinitial logical values arranged in a pattern, where the magnetic sensingarray is configured to sense an external magnetic field strength basedon a flip rate of the first initial logical values. The magnetic memorydevice further includes a voltage modulator configured to, in responseto the external magnetic field strength being greater than a thresholdmagnetic field strength, provide a test voltage different from a currentwrite voltage of the magnetic memory device. The magnetic memory devicefurther includes an error check array including a number of error checkelements with second initial logical values, where the error check arrayis configured to read the second initial logical values of the number oferror check elements, write a same logical value to each error checkelement of the number of error check elements using the test voltage asa write voltage, and compare written logical values of the number oferror check elements with the second initial logical values to calculatea bit error rate corresponding to the test voltage. The magnetic memorydevice further includes a control unit configured to adjust, based onthe bit error rate being equal to or less than a threshold bit errorrate, a write voltage of the magnetic memory device from the currentwrite voltage to the test voltage.

In some embodiments, a method for operating a magnetic memory deviceincludes sensing, by a magnetic sensing array, an external magneticfield strength and providing, in response to the external magnetic fieldstrength being greater than a threshold magnetic field strength, a testvoltage different from a current write voltage of the magnetic memorydevice. The method further includes reading initial logical values of anumber of error check elements of an error check array, writing a samelogical value to each error check element of the number of error checkelements using the test voltage as a write voltage, and comparingwritten logical values of the number of error check elements with theinitial logical values to calculate a bit error rate corresponding tothe test voltage. The method further includes adjusting, based on thebit error rate being equal to or less than a threshold bit error rate, awrite voltage of the magnetic memory device from the current writevoltage to the test voltage.

It is to be appreciated that the Detailed Description section, and notthe Abstract of the Disclosure section, is intended to be used tointerpret the claims. The Abstract of the Disclosure section may setforth one or more but not all possible embodiments of the presentdisclosure as contemplated by the inventor(s), and thus, are notintended to limit the subjoined claims in any way.

The foregoing disclosure outlines features of several embodiments sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art will appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art will also realize that suchequivalent constructions do not depart from the spirit and scope of thepresent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A magnetic memory device, comprising: a magneticsensing array configured to sense an external magnetic field strength; avoltage modulator configured to, in response to the external magneticfield strength being greater than a threshold magnetic field strength,provide a test voltage different from a current write voltage of themagnetic memory device; an error check array configured to use the testvoltage as a write voltage of the error check array and provide a biterror rate corresponding to the test voltage; and a control unitconfigured to adjust, based on the bit error rate being equal to or lessthan a threshold bit error rate, a write voltage of the magnetic memorydevice from the current write voltage to the test voltage.
 2. Themagnetic memory device of claim 1, wherein the magnetic sensing arraycomprises one or more magnetic sensing sections, and wherein eachmagnetic sensing section of the one or more magnetic sensing sections isconfigured to sense a range of external magnetic field strengths.
 3. Themagnetic memory device of claim 1, wherein the magnetic sensing arraycomprises a plurality of magnetic sensing elements with initial logicalvalues of 0 or 1 arranged in a pattern, and wherein the magnetic sensingarray is configured to sense the external magnetic field strength basedon a flip rate of the initial logical values.
 4. The magnetic memorydevice of claim 1, wherein the magnetic sensing array comprises aplurality of magnetic sensing elements, and wherein a sensitivity of themagnetic sensing array to sense the external magnetic field strength isbased on a shape and a size of each magnetic sensing element of theplurality of magnetic sensing elements and a spacing between adjacentmagnetic sensing elements.
 5. The magnetic memory device of claim 1,wherein the magnetic sensing array comprises a plurality of magneticsensing elements, wherein each magnetic sensing element of the pluralityof magnetic sensing elements comprises a circular shape, a square shape,a triangular shape, a rectangular shape, or an oval shape, wherein eachmagnetic sensing element has a width between about 10 nm and about 200nm, and wherein a spacing between adjacent magnetic sensing elements isbetween about 10 nm and about 1000 nm.
 6. The magnetic memory device ofclaim 1, wherein the test voltage is repeated between about 2 and about10000 cycles, and wherein the voltage modulator is further configuredto, based on the bit error rate being greater than the threshold biterror rate, provide an other test voltage.
 7. The magnetic memory deviceof claim 1, wherein the write voltage of the magnetic memory devicecomprises a write 0 voltage and a write 1 voltage.
 8. The magneticmemory device of claim 1, wherein the error check array comprises aplurality of error check elements with initial logical values of 0 or 1arranged in a pattern, and wherein each error check element of theplurality of error check elements comprises a magnetic data cell and areference cell.
 9. The magnetic memory device of claim 1, wherein theerror check array comprises a plurality of error check elements withinitial logical values of 0 or 1, and wherein the error check array isconfigured to: read the initial logical values of the plurality of errorcheck elements; write a same logical value to each error check elementof the plurality of error check elements using the test voltage as awrite voltage; and compare written logical values of the plurality oferror check elements with the initial logical values to calculate thebit error rate corresponding to the test voltage.
 10. The magneticmemory device of claim 1, further comprising a storage array comprisinga plurality of storage elements, wherein each storage element of theplurality of storage elements comprises a magnetic tunnel junction andone or more transistors, and wherein the magnetic tunnel junction isinterposed between two metal layers of each storage element.
 11. Amagnetic memory device, comprising: a magnetic sensing array comprisinga plurality of magnetic sensing elements with first initial logicalvalues arranged in a pattern, wherein the magnetic sensing array isconfigured to sense an external magnetic field strength based on a fliprate of the first initial logical values; a voltage modulator configuredto, in response to the external magnetic field strength being greaterthan a threshold magnetic field strength, provide a test voltagedifferent from a current write voltage of the magnetic memory device; anerror check array comprising a plurality of error check elements withsecond initial logical values, wherein the error check array isconfigured to: read the second initial logical values of the pluralityof error check elements; write a same logical value to each error checkelement of the plurality of error check elements using the test voltageas a write voltage; and compare written logical values of the pluralityof error check elements with the second initial logical values tocalculate a bit error rate corresponding to the test voltage; and acontrol unit configured to adjust, based on the bit error rate beingequal to or less than a threshold bit error rate, a write voltage of themagnetic memory device from the current write voltage to the testvoltage.
 12. The magnetic memory device of claim 11, wherein theplurality of magnetic sensing elements are arranged in one or moremagnetic sensing sections, and wherein each magnetic sensing section ofthe one or more magnetic sensing sections is configured to sense a rangeof external magnetic field strengths.
 13. The magnetic memory device ofclaim 11, wherein a sensitivity of the magnetic sensing array to sensethe external magnetic field strength is based on a shape and a size ofeach magnetic sensing element of the plurality of magnetic sensingelements and a spacing between adjacent magnetic sensing elements. 14.The magnetic memory device of claim 11, wherein the test voltage isrepeated between about 2 and about 10000 cycles, and wherein the voltagemodulator is further configured to, based on the bit error rate beinggreater than the threshold bit error rate, provide an other testvoltage.
 15. The magnetic memory device of claim 11, wherein theplurality of error check elements are arranged in a pattern, and whereineach error check element comprises a magnetic data cell and a referencecell.
 16. The magnetic memory device of claim 11, further comprising astorage array comprising a plurality of storage elements, wherein eachstorage element of the plurality of storage elements comprises amagnetic tunnel junction and one or more transistors, and wherein themagnetic tunnel junction is interposed between two metal layers of eachstorage element.
 17. A method for operating a magnetic memory device,comprising: sensing, by a magnetic sensing array, an external magneticfield strength; providing, in response to the external magnetic fieldstrength being greater than a threshold magnetic field strength, a testvoltage different from a current write voltage of the magnetic memorydevice; reading initial logical values of a plurality of error checkelements of an error check array; writing a same logical value to eacherror check element of the plurality of error check elements using thetest voltage as a write voltage; comparing written logical values of theplurality of error check elements with the initial logical values tocalculate a bit error rate corresponding to the test voltage; andadjusting, based on the bit error rate being equal to or less than athreshold bit error rate, a write voltage of the magnetic memory devicefrom the current write voltage to the test voltage.
 18. The method ofclaim 17, wherein the magnetic sensing array comprises a plurality ofmagnetic sensing elements with initial logical values, and whereinsensing the external magnetic field strength comprises sensing theexternal magnetic field strength based on a flip rate of the initiallogical values of the plurality of magnetic sensing elements.
 19. Themethod of claim 17, wherein providing the test voltage comprises:repeating the test voltage between about 2 and about 10000 cycles; andproviding, based on the bit error rate being greater than the thresholdbit error rate, an other test voltage.
 20. The method of claim 17,further comprising writing to a storage array using an adjusted writevoltage.